1. Background of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device which has a function to write selectively specified data simultaneously to memory cells corresponding to a block composed of a plurality of columns.
2. Description of the Related Art
A processing function called a block write has heretofore been utilized as a method for performing an image processing at any region on a display screen at a high speed. This processing function called the block write is the one to control writing operation for the specified data to the blocks, each block being composed of a plurality of columns, at a certain write cycle of the semiconductor memory device. Usually, I/O data supplied in a specified block cycle is not used as writing data in this block cycle, but data which has been previously supplied to be stored in a register called a color register is used.
Furthermore in a block write cycle, there is a function called a column mask function. This function called column mask function is the one, for each column of a plurality of columns, to control the writing operation to memories corresponding to I/O terminals masked by data for every column. The control is made in the following manner. For example, when data at the I/O terminal is at high level, the data is written to the column corresponding to this I/O terminal. When the data at the I/O terminal is at low level, the data is not written to the column corresponding thereto. In this column mask function, there are two methods. One is a method to use I/O data supplied at the block write as the data at the I/O terminal corresponding to each column for write controlling: the other is a method to use the I/O data held in registers called a column mask register which previously has been held the I/O data. In any of these methods, the number of the columns to which the data is simultaneously written must be less than the number of the I/O terminals.
Next, a conventional semiconductor memory device to realize the above-described writing function will be described with reference to drawings. FIG. 1 is a block diagram showing an example of a conventional semiconductor memory device which has eight I/O terminals 38 and 39 for one block, the number of columns of one column to which data is simultaneously written being eight. As shown in FIG. 1, this conventional semiconductor memory device comprises, corresponding to the I/O terminals 38 and 39, a column decode circuit 1, a column address latching circuit 2, a writing control circuit 3 including eight NMOS transistors 13, a column mask register 4 including eight registers 10, a color register 5 including eight registers 11, a Y-switch 6 including eight switches 14, a memory cells 7, a column address pre-decode circuits 15 corresponding to three subordinate column addresses, and a column address pre-decode circuits 16 corresponding to three superordinate column addresses. It is noted that the circuit corresponding to one I/O terminal of the I/O terminal 39 is illustrated, in FIG. 1, as the circuit including the writing control circuit 3 and the memory cell 7. An example of the constitution of the above-mentioned column address pre-decode circuit 15 is illustrated in FIG. 2. An example of the constitution of the above-described column address pre-decode circuit 16 is also illustrated in FIG. 3.
Referring to FIG. 1, column addresses Y0, Y1, Y3, Y4, and Y5 are supplied to corresponding column address pre-decode circuit via the column address latching circuit 2, Each of the subordinate column addresses Y0, Y1, and Y2 is supplied to corresponding one of the column address pre-decode circuits 15, and each of the superordinate column addresses Y3, Y4, and Y5 is supplied to corresponding one of the column address pre-decode circuits 16.
As shown in FIG. 2, the column address pre-decode circuit 15 consists of inverters 31, 34 and 35, and NOR gates 32 and 33. During a block write cycle, in response to the supply of a block write command signal ("H" level), the foregoing subordinate column addresses are neglected regardless of the supply of the subordinate column addresses. Concerning signals YPOT and YPON output from the inverters 34 and 35, 8 columns (one block) in which the superordinate column addresses Y3, Y4 and Y5 are equal is selected, whereby a "H" level signal is output to be supplied to the column decode circuit 1. As shown in FIG. 3, the column address pre-decode circuit 16 consists of inverters 36, 37 and 38. No block write command signal is supplied to the column address pre-decode circuit 16. Upon receipt of the superordinate column addresses Y3, Y4 and Y5, a signal at a selected level is provided to either an output terminal YPIN or an output terminal YPIT and is supplied to the column decode circuit 1.
The column address, which is provided from the column address predecode circuit 15 and 16 to supply to the column decode circuit 1, is decoded by the column decode circuit 1. Then, the column address signal at "H" level after being decoded is output therefrom as a decoded signal and supplied to the Y switch 6. Upon receipt of the decoded signal at"H" level as an input, all of the switch circuits 14 of the Y switch 6 are turned on, and corresponding to 8 column adrresses, digit lines D0, D1, D2, D3, D4, D5, D6 and D7 connected to the memory cells 7 are simultaneously selected. Specifically, in the conventional memory device, during the block write cycle, the block write command signal is supplied from the outside, and the same 8 column digit lines depending on the superordinate column addresses Y3, Y4 and Y5 are selected regardless of values of data of the column address Y0, Y1 and Y2 which are the subordinate three bits.
Furthermore, as shown in FIG. 1, the writing control operation for each of the eight columns selected in such manner is performed either by the I/O data supplied from the 8 I/O terminals 38 at the block write cycle or by the input data c0 to c7 stored in the registers 10 inside the column mask register 4, which are previously supplied from the I/O terminal 38, before the block write cycle. These data are supplied to the gates of the NMOS transistors 13 constituting the write control circuit 3. When these data are at "H" level, these NMOS transistors 13 become a turning-on state. Data d0 supplied from the one I/O terminal among the I/O terminals 39 is supplied to the memory cell 7 via the write control circuit 3, the Y switch 6, and the digit lines D1 to D7 and written thereto. Furthermore, when the foregoing data is at"L" level, data writing is not performed. At the time of this data writing control, the column address control operation for the column of the least address number among the eight columns is controlled either by the input data supplied to the I/O terminal 38-0 during the block write cycle or by the data c0 held in the register 10 of the column mask register 4. Thereafter, the control operations are performed sequentially. The column address control operation for the column of the most largest address number among the eight columns is controlled either by input data to the I/O terminal 38-7 supplied at the block write cycle or by data c7 stored in the register 10 of the column mask register 4. As described above, the column address control is controlled by data corresponding to the I/O terminal 38 allotted to the respective column addresses. Moreover, the writing data for these selected 8 columns is written to the memory cell 7 by the following two ways. First, the data supplied to the I/O terminal 39 at the time of the block write cycle is transmitted to the digit lines D0 to D7 via the write control circuit 3 and the Y switch 6 to be written to the memory cell 7. Secondly, the data d0 previously supplied from the I/O terminal 39 to the register 11 of the color register 5 to be stored therein at the time of the block write cycle is transmitted to the digit lines D0 to D7 via the write control circuit 3 and the Y switch 6 to be written to the memory cell 7.
FIG. 4 is a schematic drawing showing an example of a block write method in the case where the eight column form one block and sixty four columns are divided into eight blocks. Moreover, in this method, data writing is performed only for the column of address number 5 to 59 among the columns of address number 0 to 63. When the data writing is usually performed for the columns of address number 5 to 59 using the normal write cycle, the writing operation must be conducted by performing the normal write cycle during the 55 cycles. However, when the data writing operation is conducted using this block write cycle, the columns in the portion R in FIG. 4 are subjected to the column mask and the data writing is finished completely after performing only the block write cycle for eight cycles. Therefore, the block writing will be possible to perform the data writing operation more faster than the normal writing.
In the foregoing semiconductor memory device, the number of columns to which data are simultaneously written is constant at the time of the block write cycle. Also in the case where a certain region on the image plane is processed over a wide range, it is limited to the writing operation corresponding to the number of the columns so that the restriction to the processing capability on the image plane is made. It is impossible to realize a more increase in the processing capability.